Design-Reuse

Synopsys VCS Verilog Simulator Incorporates Breakthrough Verification Capabilities

MOUNTAIN VIEW, Calif.--(BUSINESS WIRE)--Sept. 26, 2001-- Synopsys, Inc. (Nasdaq:SNPS), the technology leader for complex IC design, today announced VCS(TM) 6.0.1, the latest release of the industry's ...
TechRepublic

Verification of Asynchronous FIFO Using System Verilog

FIFO (First In First Out) is a buffer that stores data in a way that data stored first comes out of the buffer first. Asynchronous FIFO is most widely used in the System-on-Chip (SoC) designs for data ...
EDN

Mixed-mode verification of DDR, LCD, and memory sub-systems: Verilog-AMS vs. SPICE

Editor's note: This paper is the third in a series covering the pros and cons of using a Verilog-AMS view with respect to a SPICE view for verification of SOC IP having an analog component. The first ...
EDN

Comparing Verilog-AMS vs. SPICE view usage for robust AMS Verification of Power Management Controller and Mode Transition

The SOCs produced today provide a high level of functionality, driving a wide range of applications, while becoming more and more cost effective. This means that the complexity of the SOC too is ...
Design-Reuse

NextOp Announces BugScope Assertion Synthesis for Progressive, Targeted Verification

SANTA CLARA, Calif., May 6, 2010 -- NextOp Software, Inc. today announced BugScope, the industry’s first assertion synthesis product to synthesize high quality assertions and functional coverage ...